RESP: A Robust Physical Unclonable Function Retrofittedinto Embedded SRAM ArrayYu Zheng, Maryam S. Hashemian and Swarup BhuniaCase Western Reserve University, Department of EECS, Cleveland, Ohio, 44106{yu.zheng3, mxh460, skb21}@case.eduABSTRACTPhysical Unclonable Functions (PUFs) have emerged as anattractive primitive to address diverse hardware security is-sues in Integrated Circuits (ICs). A majority of existingPUFs rely on a dedicated circuit structure for generatingchip-specific signatures, which often imposes concerns dueto area/power overhead and extra design efforts. Further-more, existing PUF-based signature generation cannot beemployed to authenticate chips already in the market. Inthis paper, we propose RESP, a novel PUF structure re-alized in embedded SRAM array, a prevalent componentin processors and system-on-chips (SOCs), with virtuallyno design modification. RESP leverages on voltage-dependmemory access failures (during write) to produce large vol-ume of high-quality challenge-response pairs. Since manymodern ICs integrate SRAM array of varying size with iso-lated power grid, RESP can be easily retrofitted into thesechips. Circuit-level simulation of 1000 chips using realis-tic process variation model shows high uniqueness of 49.2%average inter-die Hamming distance and good reproducibil-ity of 2.88% intra-die Hamming distance under temperature< 85 ? C. The device aging effect, e.g. bias temperature in-stability (BTI), results in only 4.95% estimated unstable bitsfor ten-year usage.Categories and Subject DescriptorsK.6.5 [Security and Protection]: AuthenticationGeneral TermsDesign, SecurityKeywordsHardware security, PUF, SRAM, Signature, BTI1. INTRODUCTIONIn recent years, Physical Unclonable Functions (PUFs)have been widely investigated as a security primitive of in-tegrated circuits (ICs) in variety of applications such as In-tellectual Property (IP) counter-plagiarism, chip authentica-tion and embedded system security. PUFs have obvious ad-vantages over traditional digital-key storage in a non-volatilememory (NVM). First, PUFs avoid the high cost of build-ing tamper-resistant NVM system, since any invasive attackPermission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.DAC’13, May 29 - June 07 2013, Austin, TX, USA.Copyright 2013 ACM 978-1-4503-2071-9/13/05 ...$15.00.may alter internal behavior of an IC leading to incorrect sig-natures [1]. Moreover, a PUF can produce a large amount ofchallenge-response pairs that are random and usually diffi-cult to predict, which overcome the limitation of insufficientnumber (usually only one) of digital-key storage.PUFs transform the inherent random variations in a man-ufacturing process (e.g. threshold voltage (V th ), channellength (L)) to variations in circuit-level parameters for ran-dom digital-key generation. A majority of existing PUFs re-quire dedicated circuit structures [4–6]. Apart from the sub-stantial cost in silicon area, their integration into a system-on-chip (SOC) design needs extra effort on the placement,routing and verification. On the other hand, a separateclass of relatively few PUF implementations generates sig-nature from existing on-chip structures, such as PUFs thatexploit random mismatch in inner node voltages of mem-ory elements (e.g. SRAM or Flip-Flops) [7–10]. This classof PUFs, however, often requires considerable modificationsof the original design. For example, the PUF in [7] addsfour extra transistors into each 6-T SRAM cell as twistedNOR gates for initializing the inner voltages, and a pro-grammable word line duty cycle controller is inserted intothe SRAM array in [9]. Although the PUF in [8] requiresno such modification, the residual charge in the SRAM cellseverely impacts the power-up randomness of signature, thuscompromising the quality of signature. The intrinsic PUFuses the power-up state of flip-flops in FPGA, however, itrequires altering the bit configuration procedure to retainthe values and read it out [10]. Moreover, a common disad-vantage of these PUFs is small challenge-response space andShannon entropy. The SRAM cells only generate a signaturewith the entropy of 1 bit/cell in the best case.In this paper, we propose RESP, Retrofitted EmbeddedSRAM PUF. Unlike existing PUF structures, which imple-ment a PUF either through insertion of a dedicated PUF IPin a design [4–6] or through design modifications of on-chipstructures [7–10], RESP utilizes voltage scaling induced ac-cess failures in SRAM array to generate large set of robustsignatures. It leverages on the fact that modern ICs usu-ally adopt separate power delivery network (PDN) for thefunctional blocks and embedded memory [13]. Signaturegeneration in RESP can be accomplished for practically anyIC in the market or large volume of legacy ICs with pins toexternally control the supply voltage of embedded SRAM.Furthermore, the idea of RESP can be applied during anychip design process by creating separate voltage (V DD) is-land for SRAM in a die to integrate PUF into SRAM array.RESP exploits the fact that for a set of SRAM cells inan array, under scaled supply voltage, write access failureoccurs only in specific cells in the set depending on device-level process variations. After an initial value is writtento this set at the scaled supply, the content in the SRAMcells can be read out to create a random signature for achip. Fig. 1 illustrates this approach for a typical two-dimensional SRAM array. We first initialize the cells C1,
