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    188宝金博页面版: 高速设计国外经典文献资料

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    内容提示： Hig h -Speed Backplan es Pose New Ch allen g es t o Com m s Desig n ers As b ac k p l an e s p e e d s mo v e b e y o n d 3 Gb i t / s , d e s i g n e r s wi l l e n c o u n t e r pr obl ems n ot s een at l ower r at es . For t u n at el y , t h r o u g h t h e u s e of mod el i n g t e c h n i q u e s , d e s i g n e r s c an t ac k l e t h e s e i s s u e s h e ad o n . The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.1 25-Gbi...

    文档格式：PDF | 页数：8 | 浏览次数：59 | 上传日期：2013-04-03 00:02:40 | 文档星级：
    Hig h -Speed Backplan es Pose New Ch allen g es t o Com m s Desig n ers As b ac k p l an e s p e e d s mo v e b e y o n d 3 Gb i t / s , d e s i g n e r s wi l l e n c o u n t e r pr obl ems n ot s een at l ower r at es . For t u n at el y , t h r o u g h t h e u s e of mod el i n g t e c h n i q u e s , d e s i g n e r s c an t ac k l e t h e s e i s s u e s h e ad o n . The operating data rates of current state-of-the-art backplane serial links are in the 2.5- to 3.1 25-Gbit/s range. As silicon becom es available that can support higher data rates into the 5- and 1 0-Gbit/s range, comm system designers are looking for ways to support these higher rates within their existing backplanes. I n the 5- to 1 0-Gbit/s range, the technical challenges created by phenom enon such as reflections and crosstalk increase. I n addition, new voltage- and tim ing-related challenges have arisen that typically do not exist in lower data rate ranges. These include skin effect, dielectric loss, inter-sym bol interference (I SI ), and via stub effect. To overcom e these challenges, system designers m ust develop accurate and efficient m odels for both the active and the passive com ponents of the system . Silicon vendors also need channel m odels to successfully design proper on-chip circuits for im plem enting various techniques like equalization and reflection cancellation. By m odeling the known determ inistic effects of the channel, signal-integrity related problem s can be understood, and techniques can be developed to m inim ize their im pacts. To develop a backplane m odel, individual m odels for connectors, packages, PCB traces and vias are needed. I n this article, we'll exam ine the technical challenges that m ust be overcom e to support 5- to 1 0-Gbit/s rates, and the corresponding channel m odel requirem ents. Ch an n el I m pairm en ts As the data transfer rate on the channel increases, "old" problems are exacerbated, and "new" problem s arise that must be addressed. Fig u re 1 shows the key timing and voltage related im pairm ents that m ust be addressed as data rates increase.

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