Architecture Exploration for Data Intensive ApplicationsFernando Martin del CampoUniversity of Toronto Toronto, Ontario M5S 3G4fmartin@ece.utoronto.caPaul ChowUniversity of Toronto Toronto, Ontario M5S 3G4pc@ece.utoronto.caABSTRACTThis paper presents Compass, a hardware/software simula-tor for data-intensive applications. Currently focusing onin-memory stores, the objective of the simulator is to ex-plore diverse algorithms and hardware architectures, serv-ing as an aid to design systems for applications in which theelevated rate of data transfers dictates their behaviour. In-stead of simulating the devices of a conventional computingsystem, in Compass the modules represent the stages of theprocedure to attend a request to store, retrieve, or deleteinformation in a particular memory architecture, giving thesimulator the f l exibility to test and analyze several dif f erentalgorithms, components, and ideas.The system maintains a cycle-accurate model that makesit easy to interface it with simulators of physical devicessuch as RAM memories. Under a scheme like this one, thesimulator of a physical memory in the system anchors thetiming to a realistic scenario, but the rest of the componentscan be easily modif i ed to explore alternative approaches.CCS Concepts•Computing methodologies → Simulation environ-ments; •Hardware → Simulation and emulation;•Information systems → Linked lists; B-trees; •Computersystems organization → Multicore architectures;KeywordsSimulation, architecture exploration, memory, cycle-accurate,SystemC1. INTRODUCTIONModeling and simulation are an af f ordable, highly f l exiblealternative for testing and analyzing memory and proces-sor architectures, and even for exploring less conventional,custom hardware solutions. From the perspective of the ap-plications, many dif f erent algorithms can be tested to f i ndthose that are best suited for the architecture under analysis.Permission to make digital or hard copies of all or part of this work for personal orclassroom use is granted without fee provided that copies are not made or distributedfor prof i t or commercial advantage and that copies bear this notice and the full citationon the f i rst page. Copyrights for components of this work owned by others than theauthor(s) must be honored. Abstracting with credit is permitted. To copy otherwise, orrepublish, to post on servers or to redistribute to lists, requires prior specif i c permissionand/or a fee. Request permissions from permissions@acm.org.MEMSYS ’15, October 05 - 08, 2015, Washington DC, DC, USAc ? 2015 Copyright held by the owner/author(s). Publication rights licensed to ACM.ISBN 978-1-4503-3604-8/15/10...$15.00DOI: http://dx.doi.org/10.1145/2818950.2818970However, a detailed model of a full computer system canlimit the freedom to try dif f erent approaches and novel ideas.In the end, the information that can be extracted from thesimulator could be dif f i cult to interpret and analyze, as thecomplexity generated by the interaction of the dif f erent mod-ules of the system will be embedded in the results. The pro-f i ling and log data can become as complex as the informationextracted from a physical computational system.Most simulators today are built under the assumption thatthe system being modelled will follow the von Neumann ar-chitecture. That is the case of MARSSx86 [1], that uses acycle-accurate approach, and gem5 [2], a modular simula-tor that can use multiple interchangeable CPU models. Thegem5 simulator features an event-driven memory system.Simulation based on a von Neumann paradigm works verywell for scenarios where the processor-intensive operationsdrive the execution of the applications. However, when mov-ing data across the system becomes the most time-consumingoperation, there are other architectures that could be moresuitable.To increase the freedom when exploring architectures fordata-intensive applications, this work proposes Compass, amodular simulator where the functionality of each of thecomponents is based on the stages necessary to attend arequest, and not on physical devices. In its current con-f i guration, the only module that presents a detailed imple-mentation based on existing devices is the random accessmemory, which uses the DRAMSim2 [3] memory simulator.To analyze the viability of the architectures that can be in-ferred from our simulator results, approaches like the cacheand codec model [4] can be used. Cache and codec esti-mates the cost per bit of information produced in computersystems where a processor extracts data from an storage hi-erarchy. This hierarchy consists of caches and codecs. Datais moved between dif f erent levels of caches, and if it is neces-sary, information is re-encoded when moved from one mem-ory to the next. Depending on the features of the memories,and the complexity of the codecs used, each data movementoperation is assigned an specif i c cost. The processor can beabstracted as one or more control units, and the memoryhierarchy and encoders f i t very well in data-intensive appli-cations.Compass enables the exploration of radically new andnovel architectures that are freed from the limitations of thevon Neumann paradigm. Current in-memory stores used tomanage high amounts of information, such as Memcached[5], Bigtable [6], and DynamoDB [7] are designed with theassumption that they are implemented on a traditional com-
