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    188宝金博页面版: AN 453 HardCopy II ASIC Fitting Techniques

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    内容提示： ? November 2008Altera CorporationAN 453: HardCopy II ASIC Fitting TechniquesAN-453-2.0? November 2008AN 453: HardCopy II ASIC FittingTechniquesIntroductionEngineers often use a flexible, reprogrammable Stratix?II FPGA for prototyping a project, and then transfer the design to a faster, more economical HardCopy?II ASIC for mass production. This application note describes some possible design considerations and solutions for fitting a Stratix II FPGA design into a HardCopy II ASIC.HardCopy II ASICs are l...

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    © November 2008Altera CorporationAN 453: HardCopy II ASIC Fitting TechniquesAN-453-2.0© November 2008AN 453: HardCopy II ASIC FittingTechniquesIntroductionEngineers often use a flexible, reprogrammable Stratix®II FPGA for prototyping a project, and then transfer the design to a faster, more economical HardCopy®II ASIC for mass production. This application note describes some possible design considerations and solutions for fitting a Stratix II FPGA design into a HardCopy II ASIC.HardCopy II ASICs are low-cost, high-performance 1.2-V, 90-nm ASICs with pinouts, densities, and architectures that complement Stratix II FPGAs. HardCopy II ASIC features, such as phase-locked loops (PLLs), memory, and I/O elements (IOEs), are functionally and electrically equivalent to the Stratix II FPGA features. The combination of Stratix II FPGAs for in-system prototype and design verification, HardCopy II ASICs for high-volume production, and the Quartus®II design software, provides a complete, low-risk ASIC solution.HardCopy II ASIC Compatibility with Stratix II FPGA PrototypesFor the HC210(W), HC220, and HC230 devices, there are three possible Stratix II FPGAs you can choose as the companion FPGA prototyping devices. For example, you can prototype an HC230 design using EP2S90, EP2S130, or EP2S180, depending on the design requirements for logic gates, memory, and digital signal processing (DSP) functions. You prototype the HC240 using an EP2S180.Table 1 shows Stratix II FPGA to HardCopy II ASIC compatibility.Table 1. Stratix II FPGA to HardCopy II ASIC Footprint CompatibilityHardCopy II ASICsPackagesStratix II DevicesEP2S30EP2S60EP2S90EP2S130EP2S180HC21 0W484-pin FineLine BGA (1)vvv (2)——HC21 0484-pin FineLine BGAvvv (2)——HC220672-pin FineLine BGA—v———HC220780-pin FineLine BGA——vv (2)—HC2301,020-pin FineLine BGA——vvv (2)HC2401,020-pin FineLine BGA————vHC2401,508-pin FineLine BGA————vNotes to Table 1:(1)The HC210W device uses a wire-bond package; the Stratix II FPGA prototype device uses a pin-compatible flip chip package.(2)Depending on design-specific resource use, this very aggressive die-shrink might be possible. Be sure to confirm whether or not your design is a potential candidate for such an aggressive shrink by fitting it with the Quartus II software and/or consulting an Altera® Applications Engineer.

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